Thrust II: Low-Power Emerging Nanoelectronics

The overarching goal of Thrust II is to demonstrate and leverage the latest advancements in emerging nanoscale devices (e.g. harvesters, steep slope transistors, CMOS compatible integrated ferroelectrics) to design and implement energy efficient circuits and enable energy harvesting non-volatile processors. The specific technical goals are the following:
  • Demonstrate Complementary Tunnel Transistors that beat the fundamental Boltzmann limit of 60mV/decade (kT/q) switching slope that limit supply voltage scaling today
  • Demonstrate digital and mixed mode analog circuits using complementary Tunnel FETs for future mobile SOCs consuming extremely low power
  • Implement a ferroelectric non-volatile processor that operates reliably and efficiently in an interrupted power environment performing health monitoring-related complex tasks
  • Evaluate architectural implications of non-volatile processor platform, explore most energy efficient algorithm mapping to non-volatile processor platform
Battery less, self-powered electronics capable of performing complex tasks related to sensor data fusion and predictive analytics, is going to play an increasingly important role in our modern society from personal health and wellness management standpoint. With rapid progress in low voltage steep slope transistors and embedded non-volatile memory technologies such as Ferroelectric RAM, a new generation of nonvolatile, ultra low-power microprocessors is feasible in the near future. Heterogeneous core processors employing both MOSFETs and Tunnel FETs will have a transformative impact on dim/dark processors for a range of applications from wearable computing to mobile computing to enterprise computing. ASSIST research will expand the realm of today’s volatile many core processors to the nonvolatile processors that will have transformative impact in the context of reliable computing in unreliable energy harvesting environments. Non-volatile processors have zero stand-by power, fast wake up/recovery cycles, extreme resilience to power interrupt and fine-grained dynamic power management. Taking advantage of the distributed nature of the non-volatile flip flops, the processors will be able to maintain system states during periods of power blackouts, and continue forward progress of computation tasks and can provide several orders of magnitude improvement over today’s state of the art processors. We are uniquely positioned to finally realize our long term dream of true battery-less, self-powered, autonomous electronics performing complex tasks leveraging advancements in emerging nanoscale devices.